The present invention relates to fabrication of integrated circuits.
All useful integrated circuits need to have more than one level of conductor. Some sort of interlevel dielectric is therefore necessary to separate these layers from each other, and such interlevel dielectrics are used in a tremendous variety of integrated circuit processes: NMOS, CMOS, I-squared-L, ECL, ALS, high voltage, smart power, memory, logic, analog, gate arrays, and many other families of integrated circuits all have their own particular processing and interconnect demands, but all typically use multiple patterned overlaid layers of thin-film conductors, and all accordingly need to use interlevel dielectrics to separate these conductor layers. The present invention provides an improvement in the conventional processes which is applicable nearly anywhere that interlevel dielectrics are used.
For example, in conventional NMOS technology a polysilicon thin film will be patterned to provide a first level of interconnect (and also transistor gates). A relatively thick layer of a doped silicate glass (such as phosphosilicate glass ("PSG") or borophosphosilicate glass ("BPSG")) will be deposited over this conductor level to provide the first interlevel dielectric. (This layer is also often conventionally referred to as "MLO", or multi-level oxide, although it is not a pure oxide.) Contact holes are patterned in locations which will permit the following metal layer to make electrical connections between transistors in the substrate and/or polysilicon lines. Any implant which is needed for the contact locations (e.g. to assure good ohmic contact) is done at this time, and then the interlevel dielectric is reflowed. "Reflow" means that this glass is heated to a high enough temperature that surface tension effects cause its surface to smooth out. This not only gives the glass a fairly smooth surface, but also causes its sidewalls next to the contact holes to be fairly gently sloped. Similarly, the places where the patterned polysilicon under the glass has vertical edges will not cause as sharp an edge at the upper surface of the glass: where the underlying polysilicon has a sharp edge, the glass will have a smoother slope.
These smoothing effects are highly desirable, because they permit good coverage by the overlying conductor levels. That is, in this conventional process, after the reflow process a metal (such as aluminum) will be deposited (e.g. by sputtering) and then patterned. The etch which patterns the metal layer needs to be anisotropic, to keep good control over the linewidth of this layer; but, when such anisotropic etching is used, problems can occur where the metal runs over an uneven surface. Where the metal lies on a slope (even a very narrow and localized slope), this portion of the metal will take longer to etch away than the metal on flat areas will. The steeper and higher the slope is, the more overetching time will be required; but the underlying structures will not be totally inert to the etch used to cut the metal layer, and too much overetching can damage them. Thus it is desirable not to use more overetch than is necessary to reliably remove all of the unwanted metal; but if the surface under the metal has any local slope which is steeper or higher than anticipated, the amount of overetching may suddenly turn out to be insufficient to remove all of the metal. In this case, portions of metal may remain as narrow lines running along the more steeply sloped portions of the underlying surface; such unwanted lines are known as filaments, and the prevention of filaments is consistently one of the major objectives (and often one of the major problems) in developing a process for patterning conductors, since such filaments can of course short out whatever circuit is sought to be fabricated, or introduce large amounts of unexpected parasitic capacitance, or have other adverse effects on the functionality of the circuit being fabricated.
Thus, control of the surface topography of the interlevel dielectric is critical to control of subsequent processing steps, and particularly to the avoidance of filaments in the patterning of overlying conductors.
A related problem in the prior art of interlevel dielectrics is separation of the dielectric during reflow. That is, where the MLO 10 is deposited over conductor lines 16 which are spaced apart by a certain critical distance, the as-deposited MLO 10 is likely to have a fairly steep valley 13 in its surface between the conductors 16, as shown in FIG. 3A. However, the surface tension effects during reflow may cause the MLO to separate rather than coalesce at the location of this valley 13, so that the pre-reflow valley 13 is converted into a crack 14 which cuts right through the reflowed MLO 12 (as shown in FIG. 3B), which of course can destroy the functionality of the circuit.
Another criterion for interlevel dielectrics is reduction in parasitic capacitance. The capacitance between the two conductor levels which are separated by the interlevel dielectric can be a significant component of the distributed capacitance which increases the RC time constant (and therefore degrades the propagation speed) of the conductor. Such parasitic capacitances may also be pattern-dependent, and can therefore throw a designer's modelling of his circuit completely off.
The present invention advantageously solves these problems, and provides other advantages as well, by controlling the profile of the interlevel dielectric prior to reflow. The interlevel dielectric is deposited to a thickness significantly greater than needed, and then etched back to the desired thickness. This results in a profile which is similar to that which might have been achieved by deposition of sidewall oxide filaments on the underlying conductor before the interlevel dielectric is deposited. Thus, the interlevel dielectric profile over the edges of the underlying topography is gentler before reflow than in the prior art methods, and the result is that the interlevel dielectric profile over the edges of the underlying topography is also gentler after reflow than in the prior art methods.
Another way of regarding the advantages of this process is to consider that the profile of the reflowed interlevel dielectric is less sensitive to the topography of the underlying layer: that is, the sensitivity to process and design variations has been decreased. The risk of filament formation has been greatly decreased, and the reliability of any process using multiple conductor layers can therefore be increased.
Another advantage of the present invention is that thinning of the dielectric near the upper corners of the underlying patterned conductor layer is decreased. This occurs because extra interlevel dielectric material is present in close proximity to these corners before reflow, so not as much of the lateral transport of material (which normally occurs during reflow, as shown by arrows in FIGS. 2 and 4, to partially fill up the low points adjacent to a high point) is drawn from the material above these corners. Moreover, the total volume of material before reflow near an edge of the underlying conductor is greater than in the prior art, and therefore the average thickness of the interlevel dielectric material after reflow will also be greater in this region. The parasitic capacitance between the underlying and overlying levels of conductors is particularly sensitive to the thickness of the dielectric near the corners of the underlying conductor, because of the geometry-dependent electric-field increase at corners. Thus, the increased thickness of interlevel dielectric at the corners of the patterned conductor means that parasitic capacitance between the underlying and overlying levels of conductors is reduced, which is highly desirable as discussed above.
Another advantage of the present invention is that the problem of separation of the dielectric during reflow is avoided. The present invention provides additional interlevel dielectric material, so that, instead of deep valleys 13 as shown in the prior art structure of FIG. 3A, shallower valleys 13' are formed, as shown in FIG. 3C, and the disastrous cracks 14 shown in FIG. 3B never occur.
Another way of exploiting the improved dielectric coverage provided by the present invention is to reduce the average thickness of the dielectric over flat areas. That is, for a given average thickness of the dielectric over flat areas, the present invention provides improved dielectric thickness at upper edges; and, if not all of this additional thickness at upper edges is needed, it may be possible to reduce the average thickness of the dielectric over flat areas while still preserving adequate dielectric thickness at upper edges. This may also be advantageous for various reasons, including relaxed constraints on the contact hole profiles.
Thus, a further advantage of the present invention is improved contact resistance. As seen in FIG. 5, the prior art will often restrict the conduction path adjacent to the contact to a very thin lamina around the sidewalls of the contact hole. This will increase the total series resistance of the contact somewhat, and will also decrease reliability (since electromigration effects may occur in the region of high current density). By use of the present invention, a contact cross-section as shown in FIG. 6 can be achieved instead, wherein the high-current density regions are avoided; this reduces contact series resistance and helps reliability.
Another way to regard the advantages of this class of embodiments is that the sensitivity of contact quality to contact hole profiling is reduced. That is, by reducing the total height of interlevel dielectric through which the contact hole must be cut, the chance that any steep portion of the contact hole sidewall will be high enough to cause step coverage problems is reduced.
A technique which is known in the prior art is planarization of the interlevel dielectric, using techniques such as resist etchback. (See, for example, the Adams and Capio paper in volume 128 of the Journal of the Electrochemical Society at page 423 (1981), which is hereby incorporated by reference.) However, the present invention is quite different from such techniques. For one thing, the present invention does not in fact planarize the interlevel dielectric, but merely modifies its profile while leaving it somewhat non-planar. That is, interlevel dielectric planarization will leave the interlevel dielectric substantially thicker over contacts to substrate than over contacts to polysilicon, and this means that, during the contact etching step, a very large amount of overetch will occur at the locations of contacts to polysilicon while the extra thickness over the contacts to substrate is being cleared. Avoidance of ill effects due to this local overetch requires additional process modifications and/or places additional constraints on processing. Moreover, dielectric planarization is normally not used in combination with reflow, and thus it is necessary either to use some other process to profile the contact sidewalls, or else to use some method of metal deposition which permits metal to form durable low-resistance connections along the nearly vertical sidewalls of the contact hole. (There is no inherent barrier to using reflow with planarization, but no use or teaching of this in the prior art is known to the inventors.) Again, these needs require additional process modifications and/or place additional constraints on processing.
The prior art has discussed the use of sidewall oxides at the polysilicon level: among the several motivations put forth for this have been increased dielectric thickness near the upper corners of the polysilicon lines, and generally smoother topography. See, for example, U.S. Pat. Nos. 4,234,362 to Riseman and 4,356,040 to Chatterjee et al. (TI-7379), and U.S. patent application Ser. No. 469,074 (filed Feb. 23, 1983)(TI-9455), which are hereby incorporated by reference. Thus, some of the advantages of the present invention can alternatively result from the prior art methods for formation of a separate sidewall oxide under the interlevel dielectric; formation of such a separate sidewall oxide is convenient in some processes but not in others, but the present invention is applicable to nearly any process which uses multiple layers of patterned thin-film conductors. Formation of a separate sidewall oxide requires an additional deposition step together with a timed etch of approximately 110%, so that control of the etch rate in this timed etch must be quite sensitive; but profile-modification of the interlevel dielectric in accordance with the present invention does not require any additional deposition, and requires a much less sensitive etchback step. Thus, the process of the present invention has the advantage of increased process simplicity and reproducibility over the prior art methods of forming a separate sidewall oxide underneath the interlevel dielectric. Moreover, the prior art methods of forming a separate sidewall oxide underneath the interlevel dielectric are not applicable to as many processes as the present invention is.
For example, one particularly advantageous application of the present invention is in EPROM or EEPROM designs where a thick stack (of, e.g., two layers of polysilicon or silicide separated by a thin composite dielectric) is etched to have vertical sidewalls, and these stacks are laterally separated by a distance which may be nearly as small as their thickness. Under these circumstances, reliable formation of separate sidewall oxides on the stack would be difficult, unless the sidewall oxides were significantly less high than the stack, in which case many of the advantages of the sidewall oxides would be reduced. In fact, one difficulty of separate sidewall oxides generally is that they must be formed to have a height somewhat less than the height of the sidewall they adjoin, if the flat areas are to be cleared reliably. However, the present invention always provides a profile equivalent to an underlying sidewall oxide having 100% of the height of its adjacent sidewall, which is not possible with separately formed sidewall oxides. This is another advantage of the present invention.
The present invention is also particularly advantageous in the formation of interconnect structures in bipolar integrated circuits.
According to the present invention there is provided: A process for fabricating integrated circuits, comprising the steps of: providing a partially fabricated integrated circuit having a first patterned conductor layer thereon; depositing an interlevel dielectric overall; anisotropically etching said interlevel dielectric to reduce its minimum thickness by at least 10 percent; opening contact holes in said interlevel dielectric at a plurality of predetermined locations; and forming a second patterned conductor layer in a predetermined pattern.